About this role
Summary: Join the on-device AI team to deploy, compress, and optimize machine learning models for Apple silicon. You will own the end-to-end deployment pipeline, ensuring models meet strict latency, memory, and power constraints while collaborating with research and hardware teams.
Our team is new, growing, and evolving quickly, and we are hiring across multiple disciplines. We work at the intersection of machine learning, hardware, and software, creating technologies that reshape how people communicate and experience the world around them in everyday life.
We are seeking a highly skilled and motivated ML Deployment Engineer to join our on-device AI team. In this role, you will take state-of-the-art machine learning models and make them run efficiently on Apple silicon — compressing, compiling, and optimizing them to deliver intelligent experiences that run entirely on-device, with the performance, power, and privacy our users expect.
Description
On-device intelligence is at the heart of our products. Getting a model from a research checkpoint to a fast, power-efficient feature shipping on millions of devices is a deep engineering challenge that spans model compression, graph compilation, and hardware-aware optimization across the Apple Neural Engine (ANE), GPU, and CPU.
In this role, you will own the model deployment pipeline end to end: taking trained models from research and applied teams, compressing them, converting and compiling them for the target silicon, and tuning them to meet strict latency, memory, and energy budgets. You will be the owner of the entire process - from compilation to runtime on real hardware — profiling where cycles and joules are spent, diagnosing why an operation falls off the accelerator. You will be a key contributor to the entire product development lifecycle, from concept to deployment, ensuring our on-device models are fast, small, and efficient.
Responsibilities
Own the model deployment pipeline from trained checkpoint to on-device execution, ensuring models meet product-quality bars for accuracy, latency, memory, and power
Apply model compression techniques — quantization (post-training and calibration-based), palettization, pruning, and mixed-precision — and validate the accuracy/size/latency trade-offs of each
Convert and compile models to the Core ML stack and target the Apple Neural Engine, GPU, and CPU
Analyze and maximize accelerator (ANE) residency; diagnose why operations are rejected or dispatched to fallback compute units, and work with the graph to resolve them
Profile end-to-end inference on real hardware, identify bottlenecks, and optimize compute-unit placement, memory footprint, and energy consumption
Collaborate closely with ML research and applied ML to co-design models that are efficient to deploy and to feed hardware constraints back into model architecture decisions
Build and maintain tooling and automation for reproducible compression, compilation, benchmarking, and numerical validation.
Stay current with the latest advances in efficient ML inference, model compression, and accelerator architectures
Minimum qualifications
Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience
5+ years of professional experience deploying machine learning models to production, with a significant focus on on-device, edge, or otherwise resource-constrained environments
Strong programming skills in Python and C/C++
Solid understanding of deep learning fundamentals and hands-on experience with a modern ML framework (e.g., PyTorch)
Practical experience with model compression and optimization — quantization, pruning, palettization, or mixed-precision — and a working understanding of floating-point and fixed-point/integer numerics and the quality trade-offs involved
Experience taking models through a conversion and compilation toolchain to a hardware target (e.g., Core ML, TensorRT, TFLite, ONNX Runtime, or similar)
Demonstrated ability to profile and optimize code and models against strict latency, memory, and power constraints
Strong debugging skills and comfort working at the boundary between ML models, compilers, and hardware
Preferred qualifications
Hands-on experience deploying to hardware accelerators / NPUs, and familiarity with the Apple Neural Engine (ANE), GPU, and CPU compute paths
Experience with the Core ML toolchain and with inspecting or transforming model IRs (i.e MLIR) and writing custom graph passes
Familiarity with reading and reasoning about compiler analytics — diagnosing operator fallback, layout, and residency issues on an accelerator
Experience with calibration or data-based compression methods (e.g., GPTQ, activation quantization, sparsity) and layer-wise sensitivity analysis
Background in on-device LLMs or generative models, including tokenization, KV-cache, and quantized inference
Experience building benchmarking, numerical-validation, and CI tooling for model deployment
Familiarity with low-level compute kernels, SoC memory hierarchies, and hardware-software co-design
Excellent problem-solving skills, strong communication and teamwork, and a passion for building innovative products